Differences of Tasks and Functions in Verilog

Most programming languages usually use tasks and functions to execute common procedures from different places in a description. Considering the analogy of FORTRAN, tasks are similar to subroutines and functions are similar to function. Verilog provides tasks and functions to break up large behavioral designs into smaller pieces. Tasks and functions allow a designer to abstract Verilog codes that is used at many places in the design.

Tasks have input, output, and inout arguments; functions have input arguments. Thus, values can be passed into and out from tasks and functions.

Differences of Tasks and Functions

Tasks and functions serve different purpose in Verilog, and the following table describes differences between tasks and functions in Verilog. 

Functions	Tasks
can enable another function but not another task	can call or enable other tasks and functions
always execute in 0 simulation time	may execute in non-zero simulation time
must not contain delay, event, or timing control statements	may contain delay, event, wait or timing control statements
must have at least 1 input argument, or many inputs	may have no or more arguments of type input, output, or inout
always return a single value, cannot have output or inout arguments	do not return a value, but can pass multiple values through output and inout arguments

Traffic Signal Controller Using Verilog

In this session, we will design and discuss a traffic light controller using Verilog and finite state machine approach. Consider a controller for traffic at the intersection of a main street and a side street as shown in the figure beside.

To understand and get the same perception, consider the following specifications:

• The traffic signal for the main street gets highest priority because car are continuously present on the main street. Thus, the main street signal remains green by default.
• Occasionally, cars from the side street arrive at the traffic signal. The traffic signal for the side street must turn green only long enough to let the cars on the side street go.
• As soon as there are no cars on the side street, the side street traffic signal turns yellow and then red and the traffic signal on the main street turns green again.
• There is a sensor to detect cars waiting on the side street. The sensor sends a signal X as input to the controller. X = 1 if there are cars on the side street; otherwise, X = 0.
• There are delays on transitions from S1 to S2, from S2 to S3, and from S4 to S0. The delays must be controllable.

Dynamic Shift Registers

// Verilog Coding
// 16-bit dynamic shift register.
// -------------------------------------------------------------

module v_dynamic_shift_registers_1 (Q,CE,CLK,D,A);
    input CLK, D, CE;
    input [3:0] A;
    output Q;
    reg [15:0] data;

    assign Q = data[A];

    always @(posedge CLK)
    begin
        if (CE == 1'b1)
            data <= {data[14:0], D};
    end

endmodule

Verilog Coding for 1/2 Code Rate Encoder

Designing encoder in a receiver must be done before designing Viterbi decoder inside a transmitter since output of the encoder will become input of the Viterbi decoder. 

A polynomial description of a convolutional encoder describes the connections among shift registers and modulo-2 adders.  The figure beside depicts a convolutional encoder that has one input, two outputs, and two shift registers. The convolutional encoder produces two bits encoded information for each bit of input information, so it is called as a rate 1/2 encoder.

Equations of the 1/2 encoder are as follow:

        Y[0] = X[n] XOR X[n-1]

        Y[1] = X[n] XOR X[n-1] XOR X[n-2]

The following are Verilog coding for 1/2 code rate encoder that comprises two D Flip-Flops and XOR gates. 

Loops in Verilog - 2

There are four types of looping statements in Verilog: while, for, repeat, and forever. Looping statements of while and for have been discussed in the previous posting Loops in Verilog - 1, and in this session we will discuss repeat and forever loops in Verilog HDL.

Repeat Loop

The keyword repeat is used to specify this loop. The repeat loop executes the loop a fixed number of times. A repeat construct cannot be used to loop on a general logical expression. A while loop is used for that purpose. A repeat construct must contain a number, which can be constant, a variable or a signal value. However, if the number is a variable or signal value, it is evaluated only when the loop starts and not during the loop execution. The counter described in the previous discussion (Illustration 1) can be expressed with the repeat loop as shown in Illustration 2.

Loops in Verilog

There are four types of looping statements in Verilog: while, for, repeat, and forever. The syntax of these loops is very similar to the syntax of loops in the C programming language. All looping statements can appear only inside an initial or always block. Loops may contain delay expressions. 

While Loop

The keyword while is used to specify this loop. The while loop executes until the while-expression is not true. If the loop is entered when the while-expression is not true, the loop is not executed at all. Each expression can contain any operators.

Any logical expression can be specified with any operators. If multiple statements are to be executed in the loop, they must be grouped typically using keywords begin and end. Example below illustrates the use of the while loop.

Conditional Statements in Verilog

Conditional statements are used for making decisions based upon certain conditions. These conditions are used to decide whether or not a statement should be executed. Keywords if and else are used for conditional statements. There are three types of conditional statements in Verilog: No else statement, One else statement, and Nested if-else-if as shown below.

Verilog Code for Random Number Generator

The need for random number generator becomes increasingly important for information security applications such as online transactions, online banking, ATM access, and securing of private data and information.  In cryptography applications a true random number generator is necessary required to build ultimate security. To design ultimate secured encryption system as example, it demands a true random signal generator to produce key, which increases complexity to the attacker to crack it. Therefore it is important to have a random signal generator that can produce true random in information security. 

In this section we will discuss on implementation of Random Number Generator in hardware designs. In a hardware design, Random Number Generator (RNG) capabilities are required for generating a random set of test vectors. Random testing is important since if often catches hidden bugs in the digital circuit design.

Timing Checks in Verilog

In previous discussion, we discussed how to specify path delays. The purpose of specifying path delay is to simulate timing of actual digital circuit with greater accuracy than gate delays. In this section, we describe how to set up timing checks to see if any timing constraints are violated during simulation. Timing verification is particularly important for timing critical, high-speed sequential circuits such as microprocessors.

System checks are provided to do timing checks in Verilog. There are many timing check system tasks available in Verilog. All timing checks must be inside the specify blocks only. Optional notifier arguments used in these timing check system tasks are omitted to simplify the discussion.

Path Delay Modeling Using Verilog

Before reading this topic deeply, I suggest you to read the previous discussion on Timing and delay in gate level of digital circuit which is related to this topic. Various aspects of path delay modeling will be discussed in detail here. The terms pin and port are used interchangeably in this section.

1. Specify Blocks

A delay between a source (input or inout) pin and a destination (output or inout) pin of a lis called a module path delay. Path delays are assigned in Verilog within the keywords specify and endspecify. The statements within these keywords constitute a specify block.

Specify blocks contain statements to do the following:

• Assign pin-to-pin timing delays across module paths
• Set up timing checks in the circuits
• Define specparam constants

For example, we can write the module delay_OR with pin-to-pin delays, using specify blocks as follows:

Timing and Delays in Digital Circuit Designs using Verilog

Functional verification of hardware is used to verify functionality of the designed circuit. However, logic gates in real hardware have delays associated with the logic elements and paths inside. Therefore, we must also check whether the circuit design meets the timing requirements, the delay specifications for the logic designs. Checking timing requirements has become increasingly important as circuits have become smaller and faster. 

One of the beauty of Verilog is allowing the Verilog user to specify delays (Gate and pin-to-pin delays) through the logic circuits. One of the ways to check timing is to do a timing simulation that accounts for the delays associated with the block during the simulation.

Techniques other than timing simulation to verify timing have also emerged in the design automation industry. The most popular technique is static timing verification. Hardware designers first do a pure functional verification and then verify timing separately with a static timing timing verification tool. The main advantage of static verification is that it can verify timing  in orders of magnitude more quickly than timing simulation. Static timing verification is a separate field of study and is not discussed in this discussion. We will discuss in detail how timing and delays are controlled and specified in Verilog modules. Thus, by using timing simulation, hardware designer can verify both functionality and timing of the circuit with Verilog.

Types of Delay Models
There are three types of delay models used in Verilog: distributed, lumped, and pin-to-pin (path) delays.

Multiplexers and its HDL Codes

A multiplexer is like an n-position switch that selects one of its n inputs to appear on the output. A multiplexer with n inputs is called an n-to-1 Mux. The number of bits of the inputs (b) determines the size of the multiplexer. A multiplexer with n data inputs requires s = log₂(n) number of select lines to select one of the n inputs; i.e. 2^s = n.

For example, a multiplexer that selects one of its four (n = 4) 8-bit (b = 8) inputs is called an 8-bit 4-to-1 Mux. This multiplexer needs 2 select lines (s = 2). Schematic diagram of this multiplexer is shown in the figure above. This circuit can be built using an array of AND-OR gates or three-state gates wired to implement a wired-OR logic as shown in the figure below.

Multiplexers are used for data selection, bussing, parallel -to  -serial conversation, and for implementation of arbitrary logical functions. A 1-bit 2-to-1 Mux can be wired to implement NOT, AND and OR gates. Together with a NOT, 2-to-1 Mux can be used for implementation of most primitive gates. Because of this property, many FPGA cells contain multiplexers for implementing logic functions.

The following codes are Verilog codes of multiplexers:

Connecting Ports to External Signals

There are two methods of making connections between signals specified in the module instantiation and the ports in a module definition. These two methods cannot be mixed. 

1. Connecting by Ordered List
2. Connecting Ports by Name

Connecting by Ordered List

This method is the most intuitive method for most beginners. The signals to be connected must appear in the module instantiation in the same order as the ports in the port list in the module definition. 

To illustrate connecting by ordered list, assume that the module full_add4 is instantiated in the stimulus block Top. The following code is an example of illegal port connection.

-----------------------------------------------------

module Top;

//Declare connection variables

reg [3:0] A, B;

reg C_IN;

reg [3:0] SUM;

wire C_OUT;

          full_add4 fa_ordered (SUM, C_OUT, A, B, C_IN);        // instantiate full_add4, call fa0

          -

          -

          <stimulus>

          -

          -

endmodule

-------------------------------------------------------

where,
------------------------------------------------------- 

module full_add4 (sum, c_out, a, b, c_in);

output [3:0] sum; 

output c_out;

input [3:0] a, b;

input c_in;

          -

          -

          <module internals>

          -

          -

endmodule 

------------------------------------------------------- 

Notice that the external signals SUM, C_OUT, A, B, and C_IN appear in exactly the same order as the ports sum, c_out, a, b, and c_in in the module definition of full_add4.

Port Connection Rules

www..hardware-system.com

One can visualize a port as consisting of two units; internal to the module and external to the module. The internal and external units are connected as shown in the figure beside.

There are rules governing port connections when modules are instantiated within other modules. The Verilog simulator complains if any port connection rules are violated.

Inputs

Internally, input ports must always be of the type net. Externally, the input can be connected to a variable which is a reg or a net.

Outputs

Internally, outputs ports can be of the type reg or net. Externally, the outputs must always be connected to a net. They cannot be connected to a reg.

Inouts

Internally, inout ports must always be of the type net. Externally, inout ports must always be connected to a net.

Width Matching

It is legal to connect internal and external items of different sizes when making inter-module port connections. However, a warning is typically issued that the widths do not match.

Unconnected Ports

Verilog allows ports to remain unconnected. For example, certain output ports might be simply for debugging, and we might not be interested in connecting them to the external signals. We can let the port remain unconnected by instantiating a module as shown below.

 -------------------------------------------------------------------------------------------------------

          full_add4 fa0 (SUM,     , A, B, C_IN);          // Output port c_out is unconnected

--------------------------------------------------------------------------------------------------------

Example of illegal port connection

To illustrate port connection rules, assume that the module full_add4 is instantiated in the stimulus block Top. The following code is an example of illegal port connection in Verilog coding.

-----------------------------------------------------

module Top;

//Declare connection variables

reg [3:0] A, B;

reg C_IN;

reg [3:0] SUM;

wire C_OUT;

          full_add4 fa0 (SUM, C_OUT, A, B, C_IN);        // instantiate full_add4, call fa0

          -

          -

          <stimulus>

          -

          -

endmodule

-------------------------------------------------------

Illegal connection because output port SUM in the module full_add4 is connected to a register variable SUM in module Top. This problem is rectified if the variable SUM is declared as a net (wire). Read related topic on port connections more detail at Port Declaration in Verilog HDL.

Reference:

- Verilog HDL, A guide to Digital Design and Synthesis, 2nd edtion, Samir Palnitkar, SunSoft Press - A Prentice Hall Title.

Port Declaration in Verilog HDL

In the previous posting we have discussed on topic Port Connection Rules in Verilog, we suggest all of you to read that topic for better understanding with Port Declaration in Verilog. All ports in the list of ports must be declared in the module. Ports can be declared as follows:

Verilog Keyword	Type of Port
input	Input port
output	Output port
inout	Bidirectional port

Each port in the port list is defined as input, output, or inout, based on the direction of the port signal. Thus for the example of the D Flip-Flop (D_FF) in the Example 1, the port declarations are as follow:

----------------------------------------------------------------------------

                                       Example 1 (D Flip-Flop)

----------------------------------------------------------------------------

module D_FF (d,clk,q,q_bar);                     // declare parameters, variables

    input d, clk;                                            // input variables

    output q, q_bar;                                      // output variables

    wire d, clk;

     reg q, q_bar;

always @(posedge clk)                               // ---

   begin

        q <= d;                                              // Behavior block

        q_bar <= !d;

    end                                                       //

endmodule                                               

 -----------------------------------------------------------------------------

module D_FF (d,clk,q,q_bar); input d, clk; output q, q_bar; wire d, clk; reg q, q_bar; always @(posedge clk) begin q <= d; q_bar <= !d; end endmodule

 

Note that all port declarations are implicitly declared as wire in Verilog. Thus, if a port is intended to be a wire, it is sufficient to declare it as output, input, or iout. Input and inout ports are normally declared as wires. However, if output ports hold their value, they must declared as reg. For example, in the definition of D_FF module above, we want the output q to retain its value until the next positive clock edge.

Modules and Ports in Verilog HDLs

We do not discuss the basic concepts of Verilog in this blog. We assume that you already have the basic concepts of Verilog such as:

•  Lexical conventions for operators, comments, whitespace, numbers, strings, and identifier.
• Various data types are available in Verilog. There are four logic values, each with different strength levels. Available data types include nets, registers, vectors, numbers, simulation time, arrays, memories, parameters, and strings. Data types represent actual hardware elements very closely.
• Useful system tasks in Verilog to do functions such as displaying, monitoring, suspending, and finishing a simulation.
• Compiler directive `define is used to define next macros, and `include is used to include other Verilog files.

 These basic concepts lay the foundation for the material discussed in the later discussion.

Popularity of Verilog HDL

Verilog HDL has evolved as a standard hardware description language. Verilog HDL offers many useful features for hardware design. The following is some useful features of Verilog HDL.

• Verilog HDL is a general-purpose hardware description language that is easy to learn and to use. It has a similar syntax to the C programming language. Designers with C programming experience will find it easy to learn Verilog HDL.
• Verilog HDL allows different levels of abstraction to be mixed in the same model. Thus, a designer can define a hardware model in terms of switches, gates, RTL, hierarchical design or behavior code and also stimulus module as trigger signals to test the design.
• Most popular logic synthesis tools support Verilog HDL. This makes it the language of choice for designers.
• All fabrication vendors provide Verilog HDL libraries for post-logic synthesis simulation. Thus, designing a chip in Verilog HDL allows the widest choice of vendors.
• The Programming Language Interface (PLI) is a powerful feature that allows the user to write custom C code to interact with the internal data structures of Verilog. Designers can customize a Verilog HDL simulator to their needs with the PLI.

Reference:

- Verilog HDL, A guide to Digital Design and Synthesis, 2nd edtion, Samir Palnitkar, SunSoft Press - A Prentice Hall Title.

Popularity of Hardware Description Languages (HDLs)

The most popular trend currently is to design in HDL at an RTL level, because logic synthesis tools can create gate-level netlist from RTL level design. Behavioral synthesis allowed engineers to design directly in terms of algorithms and the behavior of the circuit, and then use EDA tools to do the translation and optimization in each phase of the design. However, behavior synthesis did not gain widespread acceptance. Today, RTL design continues to be very popular. Verilog HDL is also being constantly enhanced to meet the needs of new verification methodologies.

Formal verification and assertion checking techniques have emerged. Formal verification applies formal mathematical techniques to verify the correctness of Verilog HDL descriptions and to establish equivalency between RTL and gate-level netlists. However, the need to describe a design in Verilog HDL will not go away. Assertion checkers allow checking to be embedded in the RTL code. This is a convenient way to do checking in the most important parts of a design.

New verification languages combine the parallelism and hardware constructs from HDLs with the object oriented nature of C++. The languages also provide support for automatic stimulus creation, checking, and coverage which simply boost the productivity of the verification process. Verilog HDL is still needed to describe the design.

The gate-level netlist provided by logic synthesis tools is not optimal for very high-speed and timing-critical circuits like microprocessors. In such cases, designers often mix gate-level description directly into the RTL description to achieve optimum results. This practice is opposite to the high-level design paradigm, yet it is frequently used for high-speed designs because designers need to squeeze the last bit of timing out of circuits, and EDA tools sometimes prove to be insufficient to achieve the desired results.

Another technique that is used for system-level design is a mixed bottom-up methodology where the designers use either existing Verilog HDL modules, basic building blocks, or vendor-supplied core blocks to quickly bring up their system simulation. This is done to reduce development costs and compress design schedules. 

Reference:

- Verilog HDL, A guide to Digital Design and Synthesis, 2nd edtion, Samir Palnitkar, SunSoft Press - A Prentice Hall Title.