Loops in Verilog - 2

There are four types of looping statements in Verilog: while, for, repeat, and forever. Looping statements of while and for have been discussed in the previous posting Loops in Verilog - 1, and in this session we will discuss repeat and forever loops in Verilog HDL.

Repeat Loop

The keyword repeat is used to specify this loop. The repeat loop executes the loop a fixed number of times. A repeat construct cannot be used to loop on a general logical expression. A while loop is used for that purpose. A repeat construct must contain a number, which can be constant, a variable or a signal value. However, if the number is a variable or signal value, it is evaluated only when the loop starts and not during the loop execution. The counter described in the previous discussion (Illustration 1) can be expressed with the repeat loop as shown in Illustration 2.

// Illustration 1: The counter using while loop.

----------------------------------------------------------------------------

integer count;

initial 
begin
        count = 0;

        while (count < 128)         // Execute loop till count 127, exit at count 128

        begin                         
            $display("Count = %d", count);
            count = count + 1; 

        end

end  

// Illustration 2: The counter using repeat loop.

----------------------------------------------------------------------------

integer count;

initial 
begin
        count = 0;

        repeat(128)         // increment count from 0 to 127

        begin                         
            $display("Count = %d", count);
            count = count + 1; 

   end

end   

Forever Loop

The keyword forever is used to express this loop. The forever loop does not contain any expression and executes forever until the $finish task is encountered. The loop a equivalent to a while loop with an expression that always evaluates to true, e.g., while(1). A forever loop can be exited by use of the disable statement.

A forever loop is typically used in conjunction with timing control constructs. If timing control constructs are not used, the verilog simulator would execute this statement infinitely without advancing simulation time and the rest of the design would never be executed. The following example (Illustration 3 & 4) explains the use of the forever statement.

// Illustration 3: Clock Generation

// Use forever loop instead of always block

----------------------------------------------------------------------------

reg clock;

initial 
begin
        clock = 1'b0;

        forever #10 clock = ~clock;                     // Clock with period of 20 units

end                         

 

// Illustration 4: Synchronize 2 register values at every positive edge of clock

---------------------------------------------------------------------------
reg clock; 
reg clock;

initial

            forever@(posedge clock) x = y;

Reference:  

•       Verilog HDL, A guide to Digital Design and Synthesis, 2nd edtion, Samir Palnitkar, SunSoft Press - A Prentice Hall Title.
•        www.fpga-hdl.blogspot.com (image source)