CPLD Development Board

Fig.1 Top & bottom sides of Xilinx CPLD

A CPLD (Complex Programmable Logic Design) is a combination of a fully programmable AND/OR array and a bank of macrocells.The AND/OR array is reprogrammable and can perform a multiple of logic functions. Macrocells are functional blocks that perform combinatorial or sequential logic, and also have the added flexibility for true or complement, along with varied feedback paths. 

Traditionally, CPLDs have used analog sense amplifiers to boost the performance of their architectures. CPLDs perform a variety of useful functions in systems design due to their unique capabilities and as the market leader in programmable logic solutions, Xilinx provides a total solution to a designer's CPLD needs. (http://www.xilinx.com/cpld).

A lot of logic devices are hosed in a CPLD and those connections can be specified by the program (software). As an example, 7400 IC consists of 4 circuits of 2 input NAND gates that are housed inside. Another example is 7404 IC that consists of 6 circuits of inverter inside. In case of CPLD, it has wiring among the logic in the IC, so that the writing on the printed board can be made little. Detail descriptions of this could be shown in the following figure.

Fig.2 Logic gates and connections in the CPLD

CPLD has a limited capacity and the number of pins compared to FPGA. It is not better to use it in excessive expectations, this means if you has a large or complex digital circuit design the use of FPGA is suggested. The table below describes CPLD specifications of the part of the XC9500 series from Xilinx.Inc.

Parts Name	Number of Pins	Specifications
XC9536-15PC44C	44pin PLCC	2FB/36macrocells/800gates
XC9572-15PC44C	44pin PLCC	4FB/72macrocells/1600gates
XC9572-15PC84C	84pin PLCC	4FB/72macrocells/1600gates
XC95108-15PC84C	84pin PLCC	6FB/108macrocells/2400gates

The point which CPLD is convenient for is the thing about which it is possible to rewrite many times because it is recording the contents of the circuit to the flash memory. In the XC9500 series, rewriting in about 10,000 times is possible. Since the pins for the rewriting is preparatory, the contents can be rewritten in the condition to have mounted to the actual circuit if wiring is exist. The Figure 3 shows the block diagram of CPLD XC9500 series.

Parallel Execution in FPGA

Higher-performance, resource-hungry, MAC-intensive DSP algorithms may benefit from implementation within FPGA components. FPGA architectural enhancements, development tool flow advances, speed increases and cost reductions are making implementation within FPGAs increasingly attractive. FPGA technology advances include increased clock speeds, specialized DSP blocks, tool enhancements and an increasing range of intellectual property solutions. Figure above illustrates an example parallel implementation of an FIR filter within an FPGA.

The MAC operational group may be implemented in one of several different configurations within an FPGA. Three popular implementation options for the MAC operational group within an FPGA are listed below.

• Both the multiplier and the accumulator may be implemented within the logic fabric of the FPGA taking advantage of FPGA structures, such as dedicated high-speed carry chains.
• The multiplier may be implemented in an optimized multiplier block, avoiding use of FPGA fabric logic with the accumulator implemented within the logic fabric of the FPGA.
• Both the multiplier and accumulator may be implemented within an advanced multiplier block requiring the use of no FPGA logic.

Figure below illustrates the three different MAC implementation options. Each of these approaches will be heavily dependent on the architecture of the FPGA fabric, the algorithms being implemented, the performance required and the amount of functionality being implemented on the FPGA component. For example, older device families may not support the integrated accumulator function within the DSP block. In this situation, the DSP block is actually just a multiplier. Likewise, if all the DSP blocks have been used for higher-performance algorithms, it may be possible to implement implement an algorithm with no DSP blocks within the FPGA logic fabric. FPGA DSP blocks are generally implemented in either a column or row structure within the FPGA fabric.

To be continued

FPGA DSP Design Considerations

Some of the FPGA design issues that are important to signal processing algorithm implementation are discussed below. These design factors must be carefully implemented in order to achieve the highest levels of performance and fastest design implementation.

• Synchronous design implementation
• Modular project structure
• Clock boundary transitions
• Clock architecture implementation
• Critical clock and control signal routing
• Pipeline depth and structure
• Effective design constraint
• Signal processing algorithm architecture decisions
• Incorporation of debug-friendly features

This following section will discuss a few topics of the design factors mentioned above.

1. Clocking and Signal Routing

Many signal processing applications are performance limited. In other words, the faster they can run, the better. This makes the implementation of clocks and clock management critical to DSP functions. Many of the most critical signal processing operations are directly affected by the clock architecture implementation of the design. Important clock-related design factors that should be implemented with care include:

• Sufficient board-level device decoupling
• Clean low-jitter external clock sources (consider differential clock distribution for higher rate clocks)
• Careful clock source routing to the appropriate dedicated FPGA I/O pins resources
• Careful design analysis for clock function conflict

When to Use FPGAs for DSP

Potential advantages to implementing a DSP (Digital Signal Processing) function within an FPGA (Field Programmable Gate Arrays) include performance improvements, design implementation flexibility, and higher system-level integration. FPGA-based signal processing performance may be improved through a combination of design adjustments. The operational speed or data path width may be increased, and sequential operations may be made more parallel in structure. Each of these will result in higher levels of performance. When an algorithm is implemented in a structure that takes advantage of the flexibility of the target FPGA architecture, the benefits can be significant.

Typically, there are a wider range of implementation options for signal processing algorithms within an FPGA than with fixed-function components. The design team must prioritize their design objectives. For example, it may be possible to implement an algorithm as a maximally parallelized architecture, or the algorithm could be implemented within a fully serial architecture. The serial structure would require the implementation of a loop counter function within an associated hardware counter. Another design option is a hybrid approach called a semi-parallel structure. The semi-parallel structure has elements of both the full-parallel and full-serial approaches. The algorithm would be separated into multiple parallel structures; however, multiple iterations would be required through each structure for each algorithm cycle. This contrasts with the single iteration required in the full-parallel approach and the maximum number of possible iterations with the full-serial approach. Each of these algorithm implementations will have a different level of performance, design effort and resource requirements. The design team has the flexibility to optimize for size, speed, cost or a targeted combination of these factors. Algorithms may also be reconfigured to dynamically meet changing operational requirements.

What is FPGA?

Logic Cells

Field programmable gate arrays (FPGAs) are programmable digital logic chips. It means we can program them to do almost any digital function.  FPGA is a regular structure of logic cells (modules) & interconnect, which is under user’s complete control. This means that the end user can design, program, & make changes to user’s circuit whenever user wish.

FPGAs can be programmed many time we want, no limit. If we make a mistake in our design, just fix your "logic function", re-compile and re-download it. The "field programmable" portion of the FPGA's name refers to the fact that its programming takes place "in the field" (as opposed to devices whose internal functionality is hardwired by the manufacturer).

FPGAs loose their functionality when the power goes away (volatile). We have to re-download them when power goes back up to restore the functionality.

FPGAs are built from one basic "logic-cell", duplicated hundreds or thousands of time. A logic-cell is basically a small lookup table ("LUT"), a D-flipflop and a 2-to-1 mux (to bypass the flipflop if desired).

Who makes FPGAs?

There are (at least) 5 companies making FPGAs in the world. The first two (Xilinx and Altera) hold the bulk of the market.

• Xilinx invented the FPGA and is the biggest name in the FPGA world. It tends to be the density and technology leader.
• Altera is the second FPGA heavyweight, also a well-known name.
• Lattice, Actel, Quicklogic and SiliconBlue are smaller players.

FPGAs vs. microcontrollers

Are FPGAs and microcontrollers the same thing? No

• FPGAs implement programmable logic elements running in a parallel fashion.
• Microcontrollers are based on a CPU architecture (executes a set of instructions in a sequential manner).

Microcontrollers have on-chip peripherals that also execute in parallel with their CPU. But they are still much less configurable than FPGAs.

References:

1. www.xilinx.com
2. www.fpga4fun.com