Path Delay Modeling Using Verilog

Before reading this topic deeply, I suggest you to read the previous discussion on Timing and delay in gate level of digital circuit which is related to this topic. Various aspects of path delay modeling will be discussed in detail here. The terms pin and port are used interchangeably in this section.

1. Specify Blocks

A delay between a source (input or inout) pin and a destination (output or inout) pin of a lis called a module path delay. Path delays are assigned in Verilog within the keywords specify and endspecify. The statements within these keywords constitute a specify block.

Specify blocks contain statements to do the following:

• Assign pin-to-pin timing delays across module paths
• Set up timing checks in the circuits
• Define specparam constants

For example, we can write the module delay_OR with pin-to-pin delays, using specify blocks as follows:


Pin-to-pin delays in gate-level of digital design

----------------------------------------------------------------------------

module delay_OR (out, a, b, c, d);              // declare parameters, variables

    input a, b, c, d;                                         // input variables

    output out;                                               // output variables

    wire e, f;

//Specify block with path delay statements
specify

     (a => out) = 7;
     (b => out) = 7;
     (c => out) = 9;
     (d => out) = 9;  
end specify

//gate instantiations        
and a1(e, a, b);
and a2(f, c, d);
and a3(out, e, f);
                                              

endmodule                                            

----------------------------------------------------------------------------

The specify block is a separated block in the module and does not appear under any other block, such as initial or always. The meaning of the statements within specify blocks needs to be clarified.

2. Inside Specify Blocks
The statements that can be used inside specify blocks will be described in this section.

Parallel Connection

As discussed earlier, every path delay statement has a source field and a destination field. In the path delay statements shown in the example above, input a, b, c, and d are in the position of the source field and out is the destination field.

A parallel connection is specified by the symbol => and is used as shown below.

Usage: (<source_field> => <destination_field>) = <delay_value>;

In a parallel connection, each bit in the source field connects to its corresponding bit in the destination field. If the source and the destination fields are vectors, they must have the same number of bits; otherwise, there is a mismatch. Thus, a parallel connection specifies delays from each bit in source to each bit in destination.

Figure below shows how bits between the source field and destination field are connected in a parallel connection.

Verilog description of a parallel connection as follows:

Parallel connection

----------------------------------------------------------------------------

//bit-to-bit connection. both a and out are single-bit (a => out) = 7;
//vector connection. both a and out are 4-bit vectors a[3:0], out[3:0]
//a is source field, out is destination field.

(a => out) = 7;

//the above statement is shorthand notation
//for four bit-to-bit connection statements

     (a[0] => out[0]) = 7;
     (a[1] => out[1]) = 7;
     (a[2] => out[2]) = 7;
     (a[3] => out[3]) = 7;  

//illegal connection. a[4:0] is a 5-bit vector, out[3:0] is 4-bit.
//Mismatch between bit width of source and destination fields
(a => out) = 7;            // bit width does not match                                   

----------------------------------------------------------------------------

To be continued

Reference:

• Verilog HDL, A guide to Digital Design and Synthesis, 2nd edtion, Samir Palnitkar, SunSoft Press - A Prentice Hall Title.
• www.xilinx.com (source of picture)
• www.see.ed.ac.uk (source of picture)