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| Fig.1 Top & bottom sides of Xilinx CPLD |
A CPLD (Complex Programmable Logic Design) is a combination of a fully programmable AND/OR array and a bank of macrocells.The AND/OR array is reprogrammable and can perform a multiple of logic functions. Macrocells are functional blocks that perform combinatorial or sequential logic, and also have the added flexibility for true or complement, along with varied feedback paths.
Traditionally, CPLDs have used analog sense amplifiers to boost the performance of their architectures. CPLDs perform a variety of useful functions in systems design due to their unique capabilities and as the market leader in programmable logic solutions, Xilinx provides a total solution to a designer's CPLD needs. (http://www.xilinx.com/cpld).
A lot of logic devices are hosed in a CPLD and those connections can be specified by the program (software). As an example, 7400 IC consists of 4 circuits of 2 input NAND gates that are housed inside. Another example is 7404 IC that consists of 6 circuits of inverter inside. In case of CPLD, it has wiring among the logic in the IC, so that the writing on the printed board can be made little. Detail descriptions of this could be shown in the following figure.
Fig.2 Logic gates and connections in the CPLD
CPLD has a limited capacity and the number of pins compared to FPGA. It is not better to use it in excessive expectations, this means if you has a large or complex digital circuit design the use of FPGA is suggested. The table below describes CPLD specifications of the part of the XC9500 series from Xilinx.Inc.
| Parts Name | Number of Pins | Specifications |
|---|---|---|
| XC9536-15PC44C | 44pin PLCC | 2FB/36macrocells/800gates |
| XC9572-15PC44C | 44pin PLCC | 4FB/72macrocells/1600gates |
| XC9572-15PC84C | 84pin PLCC | 4FB/72macrocells/1600gates |
| XC95108-15PC84C | 84pin PLCC | 6FB/108macrocells/2400gates |
The point which CPLD is convenient for is the thing about which it is possible to rewrite many times because it is recording the contents of the circuit to the flash memory. In the XC9500 series, rewriting in about 10,000 times is possible. Since the pins for the rewriting is preparatory, the contents can be rewritten in the condition to have mounted to the actual circuit if wiring is exist. The Figure 3 shows the block diagram of CPLD XC9500 series.
