Verilog HDL

Popularity of Verilog HDL

Verilog HDL has evolved as a standard hardware description language. Verilog HDL offers many useful features for hardware design. The following is some useful features of Verilog HDL.

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Modules and Ports in Verilog HDLs

A module is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. Typically, elements are grouped into modules to provide common functionality in the design. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. This allow the designer to modify module internals without affecting the rest of the design.

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Port Declaration in Verilog HDL

All ports in the list of ports must be declared in the module. Each port in the port list is defined as input, output, or inout, based on the direction of the port signal. Note that all port declarations are implicitly declared as wire in Verilog. Thus, if a port is intended to be a wire, it is sufficient to declare it as output, input, or iout. Input and inout ports are normally declared as wires. However, if output ports hold their value, they must declared as reg.

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Port Connection Rules

One can visualize a port as consisting of two units; internal to the module and external to the module. There are rules governing port connections when modules are instantiated within other modules. The Verilog simulator complains if any port connection rules are violated.

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Connecting Ports to External Signals

There are two methods of making connections between signals specified in the module instantiation and the ports in a module definition. These two methods cannot be mixed. 

1. Connecting by Ordered List
2. Connecting Ports by Name

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