Port Declaration in Verilog HDL

In the previous posting we have discussed on topic Port Connection Rules in Verilog, we suggest all of you to read that topic for better understanding with Port Declaration in Verilog. All ports in the list of ports must be declared in the module. Ports can be declared as follows:

Verilog Keyword	Type of Port
input	Input port
output	Output port
inout	Bidirectional port

Each port in the port list is defined as input, output, or inout, based on the direction of the port signal. Thus for the example of the D Flip-Flop (D_FF) in the Example 1, the port declarations are as follow:

----------------------------------------------------------------------------

                                       Example 1 (D Flip-Flop)

----------------------------------------------------------------------------

module D_FF (d,clk,q,q_bar);                     // declare parameters, variables

    input d, clk;                                            // input variables

    output q, q_bar;                                      // output variables

    wire d, clk;

     reg q, q_bar;

always @(posedge clk)                               // ---

   begin

        q <= d;                                              // Behavior block

        q_bar <= !d;

    end                                                       //

endmodule                                               

 -----------------------------------------------------------------------------

module D_FF (d,clk,q,q_bar); input d, clk; output q, q_bar; wire d, clk; reg q, q_bar; always @(posedge clk) begin q <= d; q_bar <= !d; end endmodule

 

Note that all port declarations are implicitly declared as wire in Verilog. Thus, if a port is intended to be a wire, it is sufficient to declare it as output, input, or iout. Input and inout ports are normally declared as wires. However, if output ports hold their value, they must declared as reg. For example, in the definition of D_FF module above, we want the output q to retain its value until the next positive clock edge.

Ports of the type input and inout cannot be declared as reg because reg variables store values, and input ports should not store values but simply reflect the changes in the external signals they are connected to.

The module D Flip-Flop in Example 1 can be declared using ANSI C style syntax as follows:

----------------------------------------------------------------------------

                                       Example 2 (D Flip-Flop)

----------------------------------------------------------------------------

module D_FF (output reg q, q_bar,
                       input d, clk );                          // wire by default                          

      ---
      < module internals>
      ---                                   

endmodule                                               

-----------------------------------------------------------------------------

If the ports comprise more than 1 bit data, add the complete information together after the input and output as follow:

module D_FF (output reg q, output reg [3:0] q_bar, input  [3:0] d, input clk);   

This syntax avoids the duplication of naming the ports in both the module definition statement and the module port list definitions. If a port is declared without specifying data type, the signal will default to a wire data type.

Reference:

- Verilog HDL, A guide to Digital Design and Synthesis, 2nd edtion, Samir Palnitkar, SunSoft Press - A Prentice Hall Title.