In previous discussion, we discussed how to specify path delays. The purpose of specifying path delay is to simulate timing of actual digital circuit with greater accuracy than gate delays. In this section, we describe how to set up timing checks to see if any timing constraints are violated during simulation. Timing verification is particularly important for timing critical, high-speed sequential circuits such as microprocessors.
System checks are provided to do timing checks in Verilog. There are many timing check system tasks available in Verilog. All timing checks must be inside the specify blocks only. Optional notifier arguments used in these timing check system tasks are omitted to simplify the discussion.
