Verilog Code for Random Number Generator

The need for random number generator becomes increasingly important for information security applications such as online transactions, online banking, ATM access, and securing of private data and information.  In cryptography applications a true random number generator is necessary required to build ultimate security. To design ultimate secured encryption system as example, it demands a true random signal generator to produce key, which increases complexity to the attacker to crack it. Therefore it is important to have a random signal generator that can produce true random in information security. 

In this section we will discuss on implementation of Random Number Generator in hardware designs. In a hardware design, Random Number Generator (RNG) capabilities are required for generating a random set of test vectors. Random testing is important since if often catches hidden bugs in the digital circuit design.

Random vector generation is also used in performance analysis of chip architectures. Verilog has a system task $random that is used for generating a random number.

Usage:  $random;

             $random (<seed>);

The value of <seed> is optional and is used to ensure the same random number sequence each time the test is run. The <seed> parameter can either be a reg, integer, or time variable. The task $random returns a 32-bit signed integer. All bits, bit-selects, or part-selects of the 32-bit random number can be used as shown in the example below.

Random Number Generation

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//Generate random numbers and apply them to a simple ROM

module RNG;
integer r_seed;

reg [31;0] addr;                           // input to ROM

wire [31:0] data;                          // output from ROM
     ...
     ...

ROM rom1(data, addr);

initial

       r_seed = 2;                           //arbitrarily define the seed as 2. 

//Distributed delay in data flow definition of a module
always @(posedge clock);
       addr = $random(r_seed);       //generates random number
...
<check output of ROM against expected results>
...
....

endmodule                                            

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Reference:

• Verilog HDL, A guide to Digital Design and Synthesis, 2nd edtion, Samir Palnitkar, SunSoft Press - A Prentice Hall Title.
• www.diamondhacks.blogspot.com (source of figure)
• Another sources

Click below to download Verilog sourcecode of RNG

module RNG; integer r_seed; reg [31;0] addr; //input to ROM wire [31:0] data; // output from ROM ... ... ROM rom1(data, addr); initial r_seed = 2; //arbitrarily define the seed as 2. //Distributed delay in data flow definition of a module always @(posedge clock); addr = $random(r_seed); //generates random number ... <check output of ROM against expected results> ... .... endmodule