Modules and Ports in Verilog HDLs

We do not discuss the basic concepts of Verilog in this blog. We assume that you already have the basic concepts of Verilog such as:

•  Lexical conventions for operators, comments, whitespace, numbers, strings, and identifier.
• Various data types are available in Verilog. There are four logic values, each with different strength levels. Available data types include nets, registers, vectors, numbers, simulation time, arrays, memories, parameters, and strings. Data types represent actual hardware elements very closely.
• Useful system tasks in Verilog to do functions such as displaying, monitoring, suspending, and finishing a simulation.
• Compiler directive `define is used to define next macros, and `include is used to include other Verilog files.

 These basic concepts lay the foundation for the material discussed in the later discussion.

Modules and Ports

Learning Objective:

• Identify the components of a Verilog module definition, such as module names, port lists, parameters, variable declarations, dataflow statements, behavior statements, instantiation of other modules, and tasks or functions.
• Understand how to define the ports list for a module and declare it in Verilog.
• Describe the port connection rules in a module instantiation, and
• Understand how to connect ports to external signals, by ordered list, and by ordered name.

An easy way to understand modules and ports in Verilog is by giving a simple example. Fig. 1 shows D flip-flop circuit, and we will discuss on how write Verilog coding of this D flip-flop.

 

Fig. 1 D Flip-flop circuit

----------------------------------------------------------------------------

                                       Example 1 (D Flip-Flop)

----------------------------------------------------------------------------

module d_ff (d,clk,q,q_bar);                      // declare parameters, variables

    input d, clk;                                            // input variables

    output q, q_bar;                                     // output variables

    wire d, clk;

     reg q, q_bar;

always @(posedge clk)

   begin

        q <= d;

        q_bar <= !d;

   end

endmodule

 -----------------------------------------------------------------------------

Modules
A module is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. Typically, elements are grouped into modules to provide common functionality in the design. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. This allow the designer to modify module internals without affecting the rest of the design.

A module definition always begins with keyword module. A module definition contains an optional list of ports. The module name, port list, port declarations, and optional parameters must come first in a module definition. If the module does not exchange any signals with the environment, there are no ports in the list. Thus, port list and port declarations are present only if the module has any ports to interact with the external environment.

The endmodule statement must always come last in a module definition. All components except module, module name, and endmodule are optional, and can be mixed and matched as per design needs. Verilog allows multiple modules to be defined in a single file, and the modules can be defined in any order in the file.

To understand components of the module, let us consider a simple example of D flip-flop shown above. The D flip-flop has:

• module name: d_ff
• input ports: d & clk
• output ports: q & q_bar

The D flip-flop has a behavior block as follows:
-------------------------------------------

         always @(posedge clk)

               begin   

                        ---
                        ---

               end
 -------------------------------------------

It means the data transfer process from input q to output q will only occur during in the positive edge of clock frequency.

Ports

Ports are also referred to terminals. Ports provide the interface by which a module can communicate with its environment. The input/output pins of an IC are its ports. The input pins of d & clk and output pins of q & q_bar in the D flip-flop above are its ports. The environment can interact with the module only through its ports. The internals of the module are not visible, and can be changed without affecting the environment as long as the interface is not modified. This provides a very powerful flexibility to the designer.

Reference:

- Verilog HDL, A guide to Digital Design and Synthesis, 2nd edtion, Samir Palnitkar, SunSoft Press - A Prentice Hall Title.
- www.asic-world.com (source of figure)