VHDL

This section will discuss basic of VHDL concept for beginners. This posting is not intended as a comprehensive VHDL reference, since there are many excellent online tutorials or discussions on this topic available in internet. This section is designed to give concise and useful summary information on important language constructs and usage, -helpful and easy to use-, but not necessarily complete. This section will introduce the key concepts in VHDL and the important syntax required for most VHDL designs, particularly with reference to Field Programmable Gate Arrays (FPGAs).

One important advantage of VHDL is the ability to use multiple levels of model with different architecture.This is not unique to VHDL, and in fact Verilog does have the concept of different behavior in a single module; however, it is explicitly defined in VHDL and is extremely useful in putting together practical multi-level

Model Interface in VHDL

1. Entity Defintion
The entity defines how a design element described in VHDL connects to other VHDL models and also defines the name of the model. The entity also allows the definition of any parameters that are to be passed into the model using hierarchy.

2. Port

The method of connecting entities together is using PORTS. These are defined in the entity using the following method:

      port(
    ... list of port declarations...
      );
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Architecture: Behavioral Modelling in VHDL

1. Basic Definition of an Architecture

While the entity describes the interface and parameter aspects of the model, the architecture defines the behavior. There are several types of VHDL architecture and VHDL allows different architectures to be defined for the same entity. This is ideal for developing behavioral, Register Transfer Level RTL and gate Level architectures that can be incorporated into designs and tested using the same test benches.

The basic approach for declaring an architecture of VHDL module could be as follows

[1] If- Then - Else

The basic syntax for a simple if statement is as follows:

signal (condition) then

...statements
end if;

The condition is a Boolean expression, of the form a > b or a = b. Note that the comparison operator for equality is a single =, not to be confused with the double == used in some programming languages. For example, if two signals are equal, then set an output high would be written in VHDL as:

[1] Functions

Functions are a simple way of encapsulating behavior in a model that can be reused in multiple architectures.

[2] Packages

Packages are a common single way of disseminating type and function information in the VHDL design community.

[3] Components

While procedures, functions and packages are useful in including behavioral constructs generally, with VHDL being used in hardware design context, often there is a need to encapsulate design blocks as a separate component that can be included in a design, usually higher in the system hierarchy.