VHDL Codes for Train Controller using State Machine

Fig 1. ASM Diagram of Electric Train Controller

This posting will discuss a working example of a train controller using state machine. In this controller, two trains run counterclockwise at various speeds and avoid collisions. One train (A) runs on the outer track and the other (B) runs on the inner track. Only one train at a time is allowed to occupy the common track.

An ASM chart and State Machine diagram shown in figure 1 (above) and figure 2 contain the same information and describe algorithm of the train controller. In the ASM chart, state names, ABout, Ain, Bin, Bstop, Astop indicate the active and possible states. The rectangles contain the active (High) outputs for the given state. Outputs not listed are inactive (Low). The diamond shapes in the ASM chart indicate where the state machine tests the condition of the inputs (S1, S2, etc.). When two signals are shown in a diamond, they are both tested at the same time for the indicated values.

A state machine classic bubble diagram is shown in Figure 2 below. In the same names "in" and "out" refers to the state of track 2, the track that is common to both loops.


Description of The State Machine for Electric Train Controller

Fig. 2  State Machine Diagram of Electric Train Controller

Keyboard Codes and Commands

A host system may send 8-bit commands to the keyboard, while a keyboard may send commands and key codes to the system. System commands may be sent to the keyboard at any time. The keyboard will respond within 20 milliseconds, except when performing the basic assurance test (BAT), or executing a Reset command. The table below shows system commands and their hexadecimal values of a keyboard system. 

Command	Hex
Set/Reset Status Indicators	ED
Echo	EE
Invalid Command	EF
Select Alternate Scan Codes	F0
Invalid Command	F1
Read ID	F2
Set Typematic Rate/Delay	F3
Enable	F4
Default Disable	F5
Set Default	F6
Set All Keys - Typematic - Make/Break - Make -Typematic/Make/Break	F7 F8 F9 FA
Set Key Type - Typematic - Make/Break - Make	FB FC FD
Resend	FE
Reset	FF

Keyboard Interface Design

This section discusses a keyboard interface for reading scan data from the keyboard and producing ASCII codes of the keys pressed. The interface only handles data transmission from the keyboard. The interface reads serial data from the keyboard, detects the Make code when a key is pressed and looks up the Make code in an ASCII conversion table. For simplicity, the look-up table only handles upper-case characters.

Collecting the Make Code

The first part of the interface connects to the keyboard data and clock lines and when a key is pressed, it outputs an 8-bit scan code. The KBdata, KBclock inputs are for the keyboard data and clock inputs, and the 8-bit ScanCode is the main output of this part. 

This part also uses a fast synchronizing clock, SYNclk, and a keyboard reset input, KBreset. In addition to the ScanCode output, this part outputs a signal to indicate that a scan code is ready (ScanRdy) and another output to indicate that a key has been released (KeyReleased). These outputs make distinction between Make and Break states.

Traffic Signal Controller Using Verilog

In this session, we will design and discuss a traffic light controller using Verilog and finite state machine approach. Consider a controller for traffic at the intersection of a main street and a side street as shown in the figure beside.

To understand and get the same perception, consider the following specifications:

• The traffic signal for the main street gets highest priority because car are continuously present on the main street. Thus, the main street signal remains green by default.
• Occasionally, cars from the side street arrive at the traffic signal. The traffic signal for the side street must turn green only long enough to let the cars on the side street go.
• As soon as there are no cars on the side street, the side street traffic signal turns yellow and then red and the traffic signal on the main street turns green again.
• There is a sensor to detect cars waiting on the side street. The sensor sends a signal X as input to the controller. X = 1 if there are cars on the side street; otherwise, X = 0.
• There are delays on transitions from S1 to S2, from S2 to S3, and from S4 to S0. The delays must be controllable.

Filtering and Algorithms

Digital filters are used in audio systems for attenuating or boosting the energy content of a sound wave at specific frequencies. The most common filter forms are high-pass, low-pass, band-pass and notch. Any of these filters can be implemented in two ways. These are the Finite Impulse Response (FIR) filter and the Infinite Impulse Response (IIR) filter, and they constitute building blocks to more complicated filtering algorithms like parametric equalizers and graphic equalizers.

Finite State Machine

A sequential circuit is a digital system that has memory and decisions. It makes for a given input depend on what it has memorized. These circuits have local (inside flip-flops) or global feed backs and the number of feed backs determine how much of its past history it remembers.

The number of states of a sequential circuit is determined by its memory. A circuit with n memory bits has 2n possible states. Signals or variables representing these states (n of them) are called state variables. Because sequential circuits have a finite number of states, they are also called finite state machines (FSM).

All sequential circuits from a single latch to a network of high performance computers can be regarded as an FSM. These machines can be modeled as a combinational circuit with feedback. If the feedback path includes an array of flip-flops with a clock for controlling the timing of data feeding back, the circuit becomes a synchronous sequential circuit. Figure below shows the Huffman model of synchronous sequential circuits. This model divides a circuit into a combinational part and a register part.

The clock shown is the synchronization signal. Outputs that are fed back to the inputs are state variables. The inputs of the flip-flops become the present state of the machine after the circuit clock ticks. The circuit decides on its outputs and its next state based on its inputs and its present state.



References:

• Digital Design and Implementation with Field Programmable Devices, Zainalabedin Navabi, Kluwer Academic Plubishers, 2005.