For example, a multiplexer that selects one of its four (n = 4) 8-bit (b = 8) inputs is called an 8-bit 4-to-1 Mux. This multiplexer needs 2 select lines (s = 2). Schematic diagram of this multiplexer is shown in the figure above. This circuit can be built using an array of AND-OR gates or three-state gates wired to implement a wired-OR logic as shown in the figure below.
Multiplexers are used for data selection, bussing, parallel -to -serial conversation, and for implementation of arbitrary logical functions. A 1-bit 2-to-1 Mux can be wired to implement NOT, AND and OR gates. Together with a NOT, 2-to-1 Mux can be used for implementation of most primitive gates. Because of this property, many FPGA cells contain multiplexers for implementing logic functions.
The following codes are Verilog codes of multiplexers:
4-to-1 Multiplexer (8-bit) using IF Statement
----------------------------------------------------------------------------
module v_mux_1 (a, b, c, d, s, O); // declare parameters, variables
input [7:0] a, b, c, d;
input [1:0] s; // input variables
output [7:0] O; // output variables
reg [7:0] O;
always @(a or b or c or d or s)
begin
if (s== 2'b00) O = a;
else if (s == 2'b10) O = c;
else O = d;
end
endmodule
4-to-1 Multiplexer (8-bit ) using Case Statement
----------------------------------------------------------------------------
module v_mux_2 (a, b, c, d, s, O);input [7:0] a,b,c,d;
input [1:0] s;
output [7:0] O;
reg [7:0] O;
always @(a or b or c or d or s)
begin
case (s)
2'b00 : O = a;
2'b01 : O = b;
2'b10 : O = c;
default : O = d;
endcase
end
endmodule
4-to-1 Multiplexer (8-bit ) using Tristate Buffer
----------------------------------------------------------------------------
module v_mux_3 (a, b, c, d, s, O);input [7:0] a,b,c,d;
input [3:0] s;
output [7:0] O;
assign O = s[3] ? a :1'bz;
assign O = s[2] ? b :1'bz;
assign O = s[1] ? c :1'bz;
assign O = s[0] ? d :1'bz;
endmodule
4-to-1 Multiplexer (8-bit ) with Latch
----------------------------------------------------------------------------
module v_mux_4 (a, b, c, d, s, O);input [7:0] a,b,c, d;
input [1:0] s;
output [7:0] O;
reg [7:0] O;
always @(a or b or c or d or s)
begin
if (s == 2'b00) O = a;
else if (s == 2'b01) O = b;
else if (s == 2'b10) O = c;
else if (s == 2'b11) O = d;
end
endmodule
----------------------------------------------------------------------------
And the following codes are VHDL codes of multiplexers:
4-to-1 Multiplexer (8-bit ) using IF statement
----------------------------------------------------------------------------
library ieee;use ieee.std_logic_1164.all;
entity multiplexers_1 is
port (a, b, c, d : in std_logic (7 downto 0);
s : in std_logic_vector (1 downto 0);
O : out std_logic (7 downto 0));
end multiplexers_1;
architecture archi of multiplexers_1 is
begin
process (a, b, c, d, s)
begin
if (s = "00") then O <= a;
elsif (s = "01") then O <= b;
elsif (s = "10") then O <= c;
else O <= d;
end if;
end process;
end archi;
4-to-1 Multiplexer (8-bit ) using Case statement
----------------------------------------------------------------------------
library ieee;use ieee.std_logic_1164.all;
entity multiplexers_2 is
port (a, b, c, d : in std_logic (7 down to 0);
s : in std_logic_vector (1 down to 0);
O : out std_logic (7 down to 0));
end multiplexers_1;
architecture archi of multiplexers_2 is
begin
process (a, b, c, d, s)
begin
case s is
when "00" => O <= a;
when "01" => O <= b;
when "10" => O <= c;
when others => O <= d;
end case;
end process;
end archi;
4-to-1 Multiplexer (8-bit ) using Tristate Buffers
----------------------------------------------------------------------------
library ieee;use ieee.std_logic_1164.all;
entity multiplexers_3 is
port (a, b, c, d : in std_logic (7 downto 0);
s : in std_logic_vector (3 downto 0);
O : out std_logic ()7 downto 0);
end multiplexers_3;
architecture archi of multiplexers_3 is
begin
O <= a when (s(0)='0') else 'Z';
O <= b when (s(1)='0') else 'Z';
O <= c when (s(2)='0') else 'Z';
O <= d when (s(3)='0') else 'Z';
end archi;
4-to-1 Multiplexer (8-bit ) using Tristate Buffers
use ieee.std_logic_1164.all;
entity multiplexers_4 is
port (a, b, c, d: in std_logic (7 downto 0);
s : in std_logic_vector (1 downto 0);
O : out std_logic (7 downto 0));
end multiplexers_4;
architecture archi of multiplexers_4 is
begin
process (a, b, c, d, s)
begin
if (s = "00") then O <= a;
elsif (s = "01") then O <= b;
elsif (s = "10") then O <= c;
elsif (s = "11") then O <= d;
end if;
end process;
end archi;
References:
To download sourcecode click below
port (a, b, c, d : in std_logic (7 downto 0);
s : in std_logic_vector (3 downto 0);
O : out std_logic ()7 downto 0);
end multiplexers_3;
architecture archi of multiplexers_3 is
begin
O <= a when (s(0)='0') else 'Z';
O <= b when (s(1)='0') else 'Z';
O <= c when (s(2)='0') else 'Z';
O <= d when (s(3)='0') else 'Z';
end archi;
4-to-1 Multiplexer (8-bit ) using Tristate Buffers
----------------------------------------------------------------------------
library ieee;use ieee.std_logic_1164.all;
entity multiplexers_4 is
port (a, b, c, d: in std_logic (7 downto 0);
s : in std_logic_vector (1 downto 0);
O : out std_logic (7 downto 0));
end multiplexers_4;
architecture archi of multiplexers_4 is
begin
process (a, b, c, d, s)
begin
if (s = "00") then O <= a;
elsif (s = "01") then O <= b;
elsif (s = "10") then O <= c;
elsif (s = "11") then O <= d;
end if;
end process;
end archi;
References:
- Digital Design and Implementation with Field Programmable Devices, Zainalabedin Navabi, Kluwer Academic Plubishers, 2005.
To download sourcecode click below
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