Timing Checks in Verilog

In previous discussion, we discussed how to specify path delays. The purpose of specifying path delay is to simulate timing of actual digital circuit with greater accuracy than gate delays. In this section, we describe how to set up timing checks to see if any timing constraints are violated during simulation. Timing verification is particularly important for timing critical, high-speed sequential circuits such as microprocessors.

System checks are provided to do timing checks in Verilog. There are many timing check system tasks available in Verilog. All timing checks must be inside the specify blocks only. Optional notifier arguments used in these timing check system tasks are omitted to simplify the discussion.

1. $setup and $hold Checks

$setup and $hold tasks are used to check the setup and hold constraints for a sequential element in the design. In a sequential element such as an edge-triggered flip-flop, the setup time is the minimum time the data must arrive before the active clock edge. The hold time is the minimum the data cannot change after the active clock edge. Setup and hold times are shown in figure above.

$setup Task

Setup checks can be specified with the system task $setup.

Usage: $setup (data_event, reference_event, limit);

    data_event                 Signal that is mentioned for violations

    reference_event     Signal that establishes a reference for monitoring the data_event signal

    limit                            Minimum time required for setup of data event

Violation is reported if (T[reference_event] - T[data_event]) < limit

Example of a setup check in Verilog is shown below.

----------------------------------------------------------------------------

//Setup check is set.

//clock is the reference

//data is being checked for violations

//Violation reported if  T[posedge_clk] - T[data] < 3

    specify
            $setup (data, posedge clock, 3)
    endspecify                                       
----------------------------------------------------------------------------

$hold Task

Hold checks can be specified with the system task $hold.

Usage: $hold (reference_event, data_event, limit);

     reference_event    Signal that establishes a reference for monitoring the data_event signal
  data_event                 Signal that is mentioned for violations

     limit                            Minimum time required for hold of data event

Violation is reported if (T[data_event] - T[reference_event]) < limit

Example of a hold check in Verilog is shown below.

----------------------------------------------------------------------------

//Hold check is set.

//clock is the reference

//data is being checked for violations

//Violation reported if  T[data] - T[posedge_clk] <5

    specify
            $hold (posedge clear, data, 5)
    endspecify                                       
----------------------------------------------------------------------------


2. $width Checks

Sometimes, it is necessary to check the width of a pulse.

The system task $width is used to check that the width of a pulse meets the minimum width requirement.

Usage: $width (reference_event, limit);

     reference_event        Edge-triggered event (edge transition of a signal)

     limit                                Minimum time required for hold of data event

The data_event is not specified explicitly for $width but is derived as the next opposite edge of the reference_event signal. Thus, the $width task checks the time between the transition of a signal value to the next opposite transition in the signal value.

Violation is reported if (T[data_event] - T[reference_event]) < limit

Example of a width check in Verilog is shown below.

----------------------------------------------------------------------------

//Width check is set.

//posedge of clear is the reference event

//the next negedge of clear is the data_event

//Violation reported if  T[data] - T[clk] <6

    specify
            $width (posedge clock, 6)
    endspecify                                       
----------------------------------------------------------------------------

Reference:

• Verilog HDL, A guide to Digital Design and Synthesis, 2nd edtion, Samir Palnitkar, SunSoft Press - A Prentice Hall Title.