Connecting Ports to External Signals

There are two methods of making connections between signals specified in the module instantiation and the ports in a module definition. These two methods cannot be mixed. 

1. Connecting by Ordered List
2. Connecting Ports by Name

Connecting by Ordered List

This method is the most intuitive method for most beginners. The signals to be connected must appear in the module instantiation in the same order as the ports in the port list in the module definition. 

To illustrate connecting by ordered list, assume that the module full_add4 is instantiated in the stimulus block Top. The following code is an example of illegal port connection.

-----------------------------------------------------

module Top;

//Declare connection variables

reg [3:0] A, B;

reg C_IN;

reg [3:0] SUM;

wire C_OUT;

          full_add4 fa_ordered (SUM, C_OUT, A, B, C_IN);        // instantiate full_add4, call fa0

          -

          -

          <stimulus>

          -

          -

endmodule

-------------------------------------------------------

where,
------------------------------------------------------- 

module full_add4 (sum, c_out, a, b, c_in);

output [3:0] sum; 

output c_out;

input [3:0] a, b;

input c_in;

          -

          -

          <module internals>

          -

          -

endmodule 

------------------------------------------------------- 

Notice that the external signals SUM, C_OUT, A, B, and C_IN appear in exactly the same order as the ports sum, c_out, a, b, and c_in in the module definition of full_add4.

Connecting Ports by Name

For large & complex designs where modules have, say, 50 ports, remembering the order of the ports in the module definition is impractical and error-prone. Verilog provides the capability to connect external signals to ports by the port names, rather than by position. We can connect the ports by name by instantiating the module full_add4, as follows:

-----------------------------------------------------------------------------------

// Instantiate module fa_byname and connect signals to ports by name

   full_add4 fa_byname (.c_out(C_OUT),  .sum(SUM), .b(B), .c_in(C_IN), .a(A));       

-----------------------------------------------------------------------------------

Note that we can specify the port connections in any order as long as the port name in the module definition correctly matches the external signal.

Note that only those ports that are connected to external signals must be specified in port connection by name, and unconnected ports can be dropped. For example, if the port c_out were kept to be unconnected, port c_out is simply dropped from the port list of module full_add4 as follows:

----------------------------------------------------------------------

// Instantiate module fa_byname and connect signals to ports by name

          full_add4 fa_byname (.sum(SUM), .b(B), .c_in(C_IN), .a(A));       

----------------------------------------------------------------------

Another advantage of connecting port by name is that as long as the port name is not changed, the order of ports list of a module can be rearranged without changing the port connections in module instantiation.

Reference:

- Verilog HDL, A guide to Digital Design and Synthesis, 2nd edtion, Samir Palnitkar, SunSoft Press - A Prentice Hall Title.