Timing Checks in Verilog

In previous discussion, we discussed how to specify path delays. The purpose of specifying path delay is to simulate timing of actual digital circuit with greater accuracy than gate delays. In this section, we describe how to set up timing checks to see if any timing constraints are violated during simulation. Timing verification is particularly important for timing critical, high-speed sequential circuits such as microprocessors.

System checks are provided to do timing checks in Verilog. There are many timing check system tasks available in Verilog. All timing checks must be inside the specify blocks only. Optional notifier arguments used in these timing check system tasks are omitted to simplify the discussion.

Path Delay Modeling Using Verilog

Before reading this topic deeply, I suggest you to read the previous discussion on Timing and delay in gate level of digital circuit which is related to this topic. Various aspects of path delay modeling will be discussed in detail here. The terms pin and port are used interchangeably in this section.

1. Specify Blocks

A delay between a source (input or inout) pin and a destination (output or inout) pin of a lis called a module path delay. Path delays are assigned in Verilog within the keywords specify and endspecify. The statements within these keywords constitute a specify block.

Specify blocks contain statements to do the following:

• Assign pin-to-pin timing delays across module paths
• Set up timing checks in the circuits
• Define specparam constants

For example, we can write the module delay_OR with pin-to-pin delays, using specify blocks as follows: