Entity: Interface Model in VHDL

1. Entity Definition

The entity defines how a design element described in VHDL connects to other VHDL models and also defines the name of the model. The entity also allows the definition of any parameters that are to be passed into the model using hierarchy. Figure beside is overall structure of a VHDL module. 

The basic template for an entity is as follows:

     entity <name> is 

          ...

     entity <name>;
  
If the entity has the name "test", then the entity template could be either: 

     entity test is
     end entity test; 

or:
      entity test is
     end test;

2. Ports

The method of connecting entities together is using PORTS. These are defined in the entity using the following method:

      port(
      ... list of port declarations...
      );

The port declaration defines the type of connection and direction where appropriate. For example, the port declaration for an input bit called in1 would be as follows:
      in1 : in bit;

And if the model had two inputs (in1 and in2) of type bit and a single output (out1) of type bit, then the declaration of the two ports would be as follows:

      port(
           in1, in2 : in bit;
           out1 : out bit
         );

As the connection points between entities are effectively the same as those inter-process connections, they are effectively signals and can be used as such within the VHDL of the model.

3. Generics

If the model has a parameter, then this is defined using generics. The general declaration of generics is shown below:

      generic(
      ... list of port declarations...
      );

In the case of generics, the declaration is similar to that of a constant with the form as shown below:

      param1 : integer := 4;

Taking an example of a model that had two generics (gain (integer) and time_delay (time)), they could be defined in the entity as follows:

      generic(
           gain : integer := 4;
           time_delay : time = 10 ns
         );

4. Constants

It is also possible to include model specific constants in the entity using the standard declaration of constants method, for example:
          
      constant : rpullup : real := 1000.0;

    

5. Entity Examples

To illustrate a complete entity, we can bring together the ports and generics examples previously and construct the complete entity for this example:

      entity test is(
      port(
           in1, in2 : in bit;
           out1 : out bit
         );

      generic(
           gain : integer := 4;
           time_delay : time = 10 ns
         );            constant : rpullup : real := 1000.0;
    
     end entity test;

References:

• FPGAs World Class Designs, Clive "Max" Maxfield, Elsevier, 2009  
• http://lohsharon.wordpress.com (source of image)