FPGA DSP Design Considerations

Some of the FPGA design issues that are important to signal processing algorithm implementation are discussed below. These design factors must be carefully implemented in order to achieve the highest levels of performance and fastest design implementation.

• Synchronous design implementation
• Modular project structure
• Clock boundary transitions
• Clock architecture implementation
• Critical clock and control signal routing
• Pipeline depth and structure
• Effective design constraint
• Signal processing algorithm architecture decisions
• Incorporation of debug-friendly features

This following section will discuss a few topics of the design factors mentioned above.

1. Clocking and Signal Routing

Many signal processing applications are performance limited. In other words, the faster they can run, the better. This makes the implementation of clocks and clock management critical to DSP functions. Many of the most critical signal processing operations are directly affected by the clock architecture implementation of the design. Important clock-related design factors that should be implemented with care include:

• Sufficient board-level device decoupling
• Clean low-jitter external clock sources (consider differential clock distribution for higher rate clocks)
• Careful clock source routing to the appropriate dedicated FPGA I/O pins resources
• Careful design analysis for clock function conflict

Signal processing functionality should be directed toward implementation within the optimized DSP blocks. If there are not enough DSP blocks to implement all of the desired signal processing functions within the available DSP blocks, then the algorithms with the highest level of required performance or largest amount of equivalent logic constraints can be used to guide the tools to place the desired functionality within the appropriate dedicated FPGA resources.

The design implementation layout or report file should be regularly checked to verify that the targeted functionality has been placed into the correct FPGA resources. This also applies to math function related signal routing such as carry logic. While the tools to regular priority logic fabric routing which can significantly reduce the level of performance which can be achieved.

2. Pipelining

Pipelining is an essential element of implementing high-speed signal processing algorithms. The register-rich nature of FPGA architectures naturally supports register-intensive algorithm implementations. The efficient implementation of signal processing algorithms within FPGA components is based on efficient implementation of the low-level algorithm arithmetic operations. These operations may be separated from each other by registers. The addition of registers in between math operations allows higher speeds of operation. Adding registers to the design will result in a "deeper" pipeline through the design. The resource penalty of additional registers allows the highest level of performance possible.

3. Algorithm Implementation Choices

The wide range of potential algorithm implementation options with FPGA components will require the design team to run a number of design trade-off studies. The most important design factors affecting DSP block resource allocation include the number of algorithms, which can benefit from DSP blocks, the number of available DSP blocks and associated block memories, the level of performance required for individual algorithms and the type of algorithm implemented. 

Another design factor is how algorithm coefficients will be used and stored within the design. For fully-serial and semi-parallel  algorithm implementations, if fixed coefficients are required, then shift registers may be used to store the coefficients saving valuable block memory resources for other functions. The design team will need to make architectural decisions regarding full-serial, semi-parallel or full-parallel for individual algorithm implementations since the tools may not be able to efficiently find an optimized implementation solution. A final consideration is to ensure that all the available DSP blocks have been used. Implementing functionality within the DSP blocks results in higher performance and lower power consumption.

4. DSP Intellectual Property (IP)

There are a wide range of potential signal processing algorithms. Some of the most popular functions have been implemented as intellectual property blocks.

References:

- FPGAs World Class Designs, Clive "Max" Maxfield, Elsevier, 2009, p 317-320 -  www.eetimes.com (source of image)