Architecture: Behavioral Modelling in VHDL

1. Basic Definition of an Architecture

While the entity describes the interface and parameter aspects of the model, the architecture defines the behavior. There are several types of VHDL architecture and VHDL allows different architectures to be defined for the same entity. This is ideal for developing behavioral, Register Transfer Level RTL and gate Level architectures that can be incorporated into designs and tested using the same test benches.

The basic approach for declaring an architecture could be as follows:

 
     architecture behaviour of test is

         ..architecture declarations

         

      begin

          ..architecture contents

     end architecture behaviour;

Or

          
     architecture behaviour of test is

          ..architecture declarations

      

      begin

          ..architecture contents

        

     end behaviour;

 

2. Architecture Declaration Section

After the declaration of the architecture name and before the begin statement, any local signals or variables can be declared. For example, if there were two internal signals to the architecture called sig1 and sig2, they could be declared in the declaration section of the model as follows:

     architecture behaviour of test is

          signal sig1, sig2 : bit;

      

      begin

Then the signals can be used in the architecture statement section.

3. Architecture Statement Section

VHDL architectures can have a variety of structures to achieve different types of functionality. Simple combinatorial expressions use signal assignments to set new signal values as shown below:

      out1 <= in1 and in2 after 10 ns;

Note that for practical design, the use of the "after 10 ns" is not synthesizable. In practice, the only way to ensure correct synthesizable design is to earlier make the design delay insensitive or synchronous. The design of combinatorial VHDL will result is additional delays due to the technology library gate delays, potentially resulting in glitches or hazards. An example of a multiple gate combinatorial architecture using internal signal declarations is given below:

          

     architecture behaviour of test is

          signal int1, int2 : bit;

      

      begin

          int1 <= in1 and in2;

          int2 <= in3 and in4;

          out1 <= int1 xor int2;

     end architecture behavioural;

References:

• FPGAs World Class Designs, Clive "Max" Maxfield, Elsevier, 2009  
• http://www.dolphin.fr (source of image)