Basic Variable Types and Operators in VHDL

This section will discuss on Constants, Signals, Variables, Boolean Operators, Arithmetic Operators, Comparison Operators, Shifting Functions and Concatenation in VHDL.

[1]. Constants

Element type of constants will be used when a value needs to be static throughout a simulation. Constants often used to initialize parameters or to set fixed register values for comparison. A constant can be declared for any defined type in VHDL with examples as follows;

     constant a : integer := 1;

     constant b : real := 0.123;

     constant c : std_logic := `0';    

[2]. Signals

Signals are the link between processes and sequential elements within the processes. Signals are effectively "wires" in the design and connect all the design elements together.

Signals can be assigned immediately or with a time delay, so that an event is scheduled for sometime in the future (after the specified delay). It is also important to recognize that signals are not the same as a set of sequential program code, but are effectively concurrent signals that will not be able to be considered stable until the next time the process is activated.

Examples of signal declaration and assignment are shown below:

     

     signal sig1 : integer := 0;

     signal sig2 : integer := 1;

     sig1 <= 14; 

     sig1 <= sig2; 

     sig1 <= sig2 after 10 ns;  

[3]. Variables

While signals are the external connections between processes, variables are the internal values within a process. They are only used in a sequential manner, unlike the concurrent nature of signals within and between processes. Variables are used within processes and are declared and used as follows:

     

     variable var1 : integer := 0;

     variable var2 : integer := 1;

     var1 := var2;  

     

Notice that there is no concept of a delay in the variable assignment, if you need to schedule an event, it is necessary to use a signal.

[4]. Boolean Operators

VHDL has a set of standard Boolean operators built in, which are self-explanatory. The list of operators are and, or, nand, not, nor, xor. These operators can be applied to BIT, BOOLEAN or logic types with examples as follows:

     

     out1 <= in1 and in2;

     out2 <= in3 or in4;

     out5 <= not in5; 

     

[5]. Arithmetic Operators

There are a set of arithmetic operators built into VHDL which again are self-explanatory and these are described and examples provided as shown in the table below.

Operator	Description	Example
+	Addition	out1 <= in1 + in2;
-	Subtraction	out1 <= in1 - in2;
*	Multiplication	out1 <= in1 * in2;
/	Division	out1 <= in1/in2;
abs	Absolute Value	absin1 <= abs(in1);
mod	Modulus	modin1 <= mod(in1);
rem	Remainder	remin1 <= rem(in1);
**	Exponent	out1 <= in1 ** 3;

[6]. Comparison Operators

VHDL has a set of standard comparison operators built in, which are self-explanatory. The list of operators are =, /=, <, <=, >, >=. These operators can be applied to a variety of types as follows:

     in1 < 1

     in2 /= in2

     in2 >= 0.4

[7]. Shifting Functions

VHDL has a set of six built-in logical shift functions which are summarized in the table as follows:

Operator	Description	Example
sll	Shift Left Logical	reg <= reg sll 2;
srl	Shift Right Logical	reg <= reg srl 2;
sla	Shift Left Arithmetic	reg <= reg sla 2;
sra	Shift Right Arithmetic	reg <= reg sra 2;
rol	Rotate Left	reg <= reg rol 2;
ror	Rotate Left	reg <= reg ror 2;

[8]. Concatenation

The concatenation function XE "VHDL:concatenation" in VHDL is denoted by the & and symbol and is used as follows:

     A <= `1111';

     B <= `000';

     out1 <= A & B & `1';   -out1 = `11110001';

References:

• FPGAs World Class Designs, Clive "Max" Maxfield, Elsevier, 2009  
• http://docstoc.com (source of image)