Hierarchical Design in VHDL

[1] Functions 

Functions are a simple way of encapsulating behavior in a model that can be reused in multiple architectures. Functions can be defined locally to an architecture or more commonly in a package, but in this section the basic approach of defining functions will be described. The simple form of a function is to define a header with the input and output variables as shown below:

      function name (input declarations) return output_type is

           ... variable declarations
      begin

           ... function body

      end

For example, a simple function that takes two input numbers and multiplies them together could be defined as follows:

             

      function mult (a, b: integer) return integer is

      begin

           return a * b;

      end; 

[2] Packages 

Packages are a common single way of disseminating type and function information in the VHDL design community. The basic definition of a package is as follows:

      package name is

           ... package header contents
      end package;
      package body name is
      begin

           ... package body contents

      end package body;

As can be seen, the package consists of two parts, the header and the body. The header is the place where the types and functions are declared, and the package body is where the declarations themselves take place.

For example, a function could be described in the package body and the function is declared in the package header. Take a simple example of a function used to carry out a simple logic function:

      and10 = and(a, b, c, d, e, f, g, h, i, j)

The VHDL function would be something like the following:

      function and10 = and(a,b,c,d,e,f,g,h,i,j: bit) return bit is 
      begin

        return a and b and c and d and e and f and g and h and i and j;

      end;

The resulting package declaration would then use the function in the body and the function header in the package header thus:
   
      package new_functions is 
      function and10 = and(a,b,c,d,e,f,g,h,i,j: bit) return bit;
      end;
      package body new_functions is       
         function and10 = and(a,b,c,d,e,f,g,h,i,j: bit) return bit is;
           begin

              return a and b and c and d and e \ 
                  and f and g and h and i and j;

           end;
      end;

[3] Components

While procedures, functions and packages are useful in including behavioral constructs generally, with VHDL being used in hardware design context, often there is a need to encapsulate design blocks as a separate component that can be included in a design, usually higher in the system hierarchy.

To be continued

[4] Procedures

Procedures are similar to functions, except that they have more flexibility in the parameters, in that the direction can be in.

To be continued