Modeling Memories: Memory Arrays

Memories are among the most frequently modeled components. How they are modeled can determine not just the performance, but the very practicality of board-level simulation. 

Many board have memory on them, and FPGA designs frequently interface to one or more types of memory. These are not the old asynchronous static RAMs of more innocent times. These memories are pipelined zero bus turnaround (ZBT) synchronous static RAMs (SSRAM), multibanked synchronous dynamic RAMs (SDRAM), or double data rate (DDR) DRAMs. The list goes on and complexities go up. Verify the interfaces or face the consequences.

Just as the memories have become complex, so have the models. There are several issues specific to memory models. How they are dealt with will determine the accuracy, performance, and resource requirements of the models.

Memory Arrays

There are a number of ways memory arrays can be modeled. The most obvious and commonly used is array of bits. This is the method that most closely resembles the way a memory component is constructed. Because the model's ports are of type std_logic, we can create an array of type std_logic_vector for our memory:

   TYPE MemStore IS ARRAY (0 to 255) OF STD_LOGIC_VECTOR (7 DOWNTO 0);

This has the advantage of allowing reads and writes to the array without any type conversions. However, using an std_logic_vector array is expensive in terms of simulation memory. std_logic is a 9-value type, which is more values than we need or can use. A typical VHDL simulator will use 1B of simulation memory for each std_logic bit. A 1 megabit memory array will consume about 1 MB of computer memory. At that rate, the amount of memory in a design can be too large to simulate.

In real hardware, memory can contain only 1s and 0s. That might suggest the use of type bit_vector, but the point of simulation is to debug and verify a design in an environment that makes it easier than debugging real hardware. It is useful if a read from a memory location that has never been written to give a unique result. Although real hardware may contain random values, 'U' s are more informative for simulation because they make it easy to see that an uninitialized location has been accessed. 

Likewise, if a timing violation occurs during a memory write, the simulation model usually emits a warning message. Ideally that location should also contain an invalid word that is recognizable as such. On reading that corrupt location, the user should see 'X' s.

So it seems type UX01 would provide all the values required. We could declare our memory array:

   TYPE MemStore IS ARRAY (0 to 255) OF UX01_VECTOR (7 DOWNTO 0);

Unfortunately, because UX01 is a subtype of std_logic, most simulators use the same amount of space to store type UX01 as they do to store std_logic.

This chapter comes to us from the book ASIC and FPGA Verification by Richard Munden.

References:

- FPGAs World Class Designs, Clive "Max" Maxfield, Elsevier, 2009

- Source of the picture from http://www.rtcmagazine.com/articles/view/102356