Memory Arrays

One option for modeling memories is the Shelor method. In 1996, Charles Shelor wrote an article in the VHDL Times as part of his "VHDL Designer" column [1], in which he discussed the problem of modeling large memories. He described several possible storage mechanisms. The method presented here is the one he favored.

The Selor Method

Shelor noted that by converting the vector to a number of type natural we can store values in much less space. Of course, there are limitations. The largest integer guaranteed by the VHDL standard is 231 - 1, meaning a 30-bit word is the most you can safely model. It turns out this is not a problem. Few memory components use word sizes larger than 18 bits and most are either 8 or 9 bits wide.

So a range of 0 to 255 is sufficient for an 8-bit word, but that assumes every bit is either 1 or 0. It would be good to also allow words to be uninitialized or corrupted. To do so, just extend the range down to -2.

A generic memory array declaration is:
   - Memory array declaration

   TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
                    RANGE -2 TO MaxData;                       

where -2 is an uninitialized word, -1 is a corrupt word, and 0 to MaxData are valid data. This method does not lend itself to manipulation of individual bits, but that is rarely called for in a component model.

Simulators tested store integers in 4B, so each word of memory, up to 18 bits, will occupy 4B of simulator memory. This is a considerable improvement over using arrays of std_logic_vector. 


The VITAL_Memory Package

Another option is to use the VITAL_Memory package released with VITAL2000. This package has an extensive array of features specific to memory modeling, including a method of declaring a memory array that results in a specific form of storage. A memory using the VITAL2000 memory package is declared as follows.

     -- VITAL Memory Declaration 
     VAIABLE Memdat : VitalMemoryDataType :=
          VitalDeclareMemory (
               NoOfWords                   =>  TotalLOC,
               NoOfBitsPerWord             =>  DataWidth,
               NoOfBitsPerSubWord          =>  DataWidth,
               MemoryLoadFile              =>  MemLoadFileName,
               BinaryLoadFile              =>  FALSE
             );

In this memory modeling, a procedure call is used to create the memory array. 

The storage efficiency is very good - a 1B word occupies only 2B of memory - but this holds true only for 8-bit words. A 9-bit word occupies 4B of memory, which is the same as the Shelor Method.

This chapter comes to us from the book ASIC and FPGA Verification by Richard Munden.

References:

- FPGAs World Class Designs, Clive "Max" Maxfield, Elsevier, 2009