Accumulators

// Verilog Coding
// 4-bit Unsigned Up Accumulator with Asynchronous Clear
// -----------------------------------------------------------------

module v_accumulators_1 (C, CLR, D, Q);

    input C, CLR;
    input [3:0] D;
    output [3:0] Q;
    reg [3:0] tmp;
   
    always @(posedge C or posedge CLR)
    begin
        if (CLR)
            tmp = 4'b0000;
        else
            tmp = tmp + D;
        end
    assign Q = tmp;
endmodule


-- VHDL Coding
-- 4-bit Unsigned Up Accumulator with Asynchronous Clear
-- -----------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity accumulators_1 is
    port(C, CLR : in std_logic;
         D : in std_logic_vector(3 downto 0);
         Q : out std_logic_vector(3 downto 0));
end accumulators_1;

architecture archi of accumulators_1 is
    signal tmp: std_logic_vector(3 downto 0);
begin

    process (C, CLR)
    begin
        if (CLR='1') then
            tmp <= "0000";
        elsif (C'event and C='1') then
            tmp <= tmp + D;
        end if;
    end process;
   
    Q <= tmp;
   
end archi;